80286 Instruction Set:
The 80286 Instruction Set are upwardly compatible with that of the 8086 processor. Most of the 80286 Instruction Set are the same as the instructions of 8086. The additional instructions of 80286 processor are as follows:
- ARPL (Adjust RPL Field of Segment Selector)
- CLTS (Clear Task Switched Flag in CRO)
- LAR ( Load Access Rights Byte)
- LGDT/LIDT (Load Global/Interrupt Description Table Register)
- LLDT (Load Local Descriptor Table Register)
- LMSW (Load Machine Status Word)
- LOADALL (Load ALL Registers)
- LSL (Load Segment Limit)
- LTR (Load Task Register)
- SGDT (Store Global Descriptor Table Register)
- SIDT (Store Interrupt Descriptor Table Register)
- SLDT (Store Local Descriptor Table Register)
- SMSW (Store Machine Status Word)
- STR ( Store Task Register)
- VERR/VERW (Verify a Segment for Reading or Writing)
In this section, all new 80286 Instruction Set are explained elaborately with examples.
ARPL (Adjust Requested Privilege Level of the Selector) The ARPL instruction enables the lower privileged routines to access higher privileged routines or data. The common format of ARPL instruction is ARPI, destination, source
This instruction compares the RPL bits of ‘destination’ against ‘source’. If the RPL bits of ‘destination’ are less than ‘source’, the destination RPL bits are set equal to the source RPL bits and the zero flag is set. Otherwise, the zero flag is cleared. The example of ARPL instruction is
ARPL register, register
CLTS (Clear Task Switch Flag) The operation of CLTS instruction is to clear the task switched flag of the status flag word. This instruction is a privileged instruction to be executed at the level 0 by the operating system software.
LAR (Load Access Rights Byte) When this instruction is executed, the access rights byte of the descriptor associated with the source (Operand 2) as a selector is loaded into the higher byte of the destination register (Operand 1) and the lower byte of the operand 1 is set to 00. The zero flag is set if the load operation is successful. The format of LAR instruction is
LAR destination, source
The example of LAR instruction is LAR AX, 4000H.
LGDT(Load Global Descriptor Table) This instruction loads a value from an operand into the Global Descriptor Table (GDT) register. No flags arc affected.
The format of LGDT instruction is
LGDT source
LIDT (Load Interrupt Descriptor Table) This instruction loads a value from an operand into the Interrupt Descriptor Table (IDT) register, No flags are affected. The format of LIDT instruction is
LIDT source
LLDT (Load Local Descriptor Table) The LLDT instruction loads a value from an operand into the Local Descriptor Table Register (LDTR). This instruction is used by Operating systems. No flags are affected. The format of LLDT instruction is LLDT source. The example of LLDT instruction is
LLDT BP
LMSW (Load Machine Status Word) This instruction loads the MSW from the effective address of the operand. The example LMSW instruction is
LMSW BP; Load MSW from address DS:BP
LSL(Load Segment Limit) This instruction loads the segment limit of a selector into the destination register if the selector is valid and visible at the current privilege level. The zero flag is set, if loading is successful. Otherwise. zero flag is cleared. The format of LSL instruction is
LSL destination, source
The example of LSL instruction is LSL AX, Selector or LSL register_16, register_16.
LTR (Load Task Register) This instruction loads the current task register with the value specified in ‘source’. No flags are affected. The format of LTR instruction is
LTR source
The example of LTR instruction is LTR [5000H]
SGDT (Store Global Descriptor Table) This instruction stores the Global Descriptor Table (GDT) register into the specified operand. No flags are affected. The format of SGDT instruction is
SGDT destination
SIDT (Store Interrupt Descriptor Table) This instruction stores the Interrupt Descriptor Table (IDT) register into the specified operand. No flags are affected. The format of SIDT instruction is
SIDT destination
SMSW (Store Machine Status Word) This instruction stores the MSW to the effective address of the operand. A general protection error exception is generated, if the operand points to a write protected segment or is if invalid memory reference. The stack-fault exception is generated for stack-segment limit overrun. The example of SMSW instruction is
SMSW BP; Store MSW to address ES:BP
STR (Store Task Register) This instruction stores the current task register to the specified operand. No flags are affected. The format of STR instruction is
STR destination
The example of STR instruction is STR [5000H]
A general protection exception is generated when there is an attempt of a write operation in a write protected segment or an invalid memory reference. A stack-fault exception is generated for usual reasons.
VERR (Verify for Read) The VERR instruction sets the zero flag if the segment pointed to by the selector (a 16-bit register or a memory operand) can be read. The example of VERR instruction is VERR BP.
VERW (Verify for Write) The VERW instruction sets the zero flag if the segment pointed to by the selector (a 16-bit register or a memory operand) can be written. The example of VERW instruction is VERW MEMORY.
ENTER (Enter Procedure) This instruction modifies the stack for entry to procedure for high-level language. This instruction which is used by most of the structured high-level languages requires two operands. The format of Enter instruction is
ENTER locals, level
Operand ‘locals’ specifies the amount of storage to be allocated on the stack. ‘Level’ specifies the nesting level of the routine. No flags are affected by this instruction. Paired with the LEAVE instruction, this is an efficient method of entry and exit to procedures. The example of Enter instruction is
ENTER immed_16, immed_8
LEAVE (Leave the Procedure) The operation of LEAVE is exactly the opposite operation of ENTER instruction. This instruction is used with high-level languages to exit a procedure. When RET instruction is executed after LEAVE. it returns the control to the calling program.
BOUND (Array Index Bound Check) When this instruction is executed, the array index in the source register is checked against upper and lower bounds in memory source. The format of BOUND instruction is
BOUND source, limit
The first word located at ‘limit’ is the lower boundary and the word at ‘limit+2’ is the upper array bound. When the source value is less than or higher than the source, Interrupt 5 occurs. None of the flags are affected. The example of BOUND instructions are BOUND register_16, memory_32, and BOUND BX, memory_32
Memory_32 is a memory block starting address containing four bytes, two bytes for the starting index and the other two for ending index.
LAHF (Load Register AH From Flags) This instruction copies bits 0-7 of the flags register into AH. This includes flags AF, CF, PF, SF and ZF other bits are undefined.
AH: = SF ZF xx AF xx PF xx CF
PUSH IMD (Push Immediate) When this instruction is executed, a 16-bit immediate data is pushed to the stack after decrementing the stack pointer (SP) by 2. If the new value of SP is outside the stack segment, a stack fault exception is generated. As the new segment reference is illegal, usually a general protection exception is generated for a push operation. Flags are not affected after execution of PUSH IMD instruction.
PUSH A (Push All) After execution of PUSH A instruction, the contents of AX, CX, DX, BX, SB, BP, SI and DI are pushed onto the stack. Hence the stack pointer (SP) is decremented by 16. As the structure of the stack is Last In First Out (LIFO), the last pushed register contents appear first, in the stack memory segment. During execution of PUSH A, if the stack segment limit is overrun, a stack fault exception is generated. None of the flags are affected.
POP A (Pop All) When this instruction is executed, the contents of the registers DI, SI, BP, SP, BX, DX, CX and AX are popped from the stack in the sequence that is exactly opposite to that of pushing. No flags are affected. Exceptions are exactly the same as PUSH A instruction.
IMUL lmd-Oper When this instruction is executed, the content of AL is multiplied with a signed immediate operand and the signed 16-bit result is stored in AX. The flags CF and OF are cleared, while the AH is a sign extension of AL, else CF and OF are set. When the immediate operand is a signed 16-bit data, the contents of AX is multiplied with signed 16-bit data and the signed result is stored in DX: AX combination, with DX as MSB and AX as LSB. Other flags are undefined.
Rotate Source, Count This is a group of four instructions such as RCL, RCR, ROL, and ROR. These instructions work as in 8086, but an additional mode of count is allowed. In 8086, the count value is either 1 or CL, but in 80286 Instruction Set, the value can be an immediate count value 0 to 31 (decimal). After execution of rotate instruction. only the OF and CF flags are changed.
INS (INSB, INSW) When INS instruction is executed. a string of byte data or word from a variable port address specified only in DX will he read. The port address may he of 16 bits. No flags are affected by this instruction. The data string read by this instruction must he stored in memory at the address pointed by ES:DI, in the sequence in which they were read. After execution of INS instruction, the DI is automatically advanced depending upon the direction flag DF. The example of INS instruction is INSB ES:DI, DX.
OUTS (OUTSB/OUTSW) When OUTS instruction is executed, a string of bytes or words from the memory location specified by DS:SI will be write to a port pointed by DX. The SI is automatically incremented by 1 for byte or incremented by 2 for word operations. The example of OUTS instruction is OUTS DX, DS:SI.