Clamping Circuit:

Negative and Positive Voltage Clamping Circuits – A clamping circuit, also known as a dc restorer, changes the dc voltage level of a waveform, but does not affect its shape Consider the clamping circuit shown in Fig. 3-33.

When the square wave input is positive, diode D₁ is forward biased, and voltage equals the diode forward voltage drop (V_F).

During the positive half-cycle of the input, the voltage side of the capacitor is +V_F, while that on the left side +E. Thus, C₁ is charged with the polarity shown to a voltage,

When the input goes negative, the diode is reverse biased and has no further effect on the capacitor voltage. Also, R₁ has a very high resistance, so that it cannot discharge C₁ significantly during the negative portion of the input waveform. While the input is negative, the output voltage is the sum of the input and capacitor voltages. Since the polarity of the capacitor voltage is the same as the (negative) input, the output is,

The peak-to-peak output voltage (V_o(PP)) is the difference between the positive output peak (V_F) and negative output peak -(2E – V_F). 

It is seen that the peak-to-peak amplitude of the output waveform from the clamping circuit is exactly the same as the peak-to-peak input. Instead of the waveform being symmetrical above and below ground, however, the output positive peak is clamped at a level of +V_F.

The circuit in Fig. 3-33 is known as a negative voltage clamping circuit, because the output waveform is almost completely negative. Reversing the polarity of the diode and capacitor in Fig. 3-33 creates the positive voltage clamping circuit shown in Fig. 3­-34. As illustrated, the output waveform is clamped to keep it almost completely positive.

Output Slope:

Resistor R₁ in Figs. 3-33 and 3-34 is sometimes termed a bleeder resistor. Its function is to gradually discharge the capacitor over several cycles of input waveform, so that it can be charged to a new voltage level if the input changes. However, R₁ partially discharges the capacitor during the time that D₁ is reverse biased, and this produces a slope, or tilt (ΔV_c) on the output waveform, as illustrated in Fig. 3-35.

The tilt voltage can be calculated from a knowledge of the waveform frequency and the circuit component values. The constant-current equation for charging or discharging a capacitor may be applied,

Component Determination:

When designing a clamping circuit, capacitor C₁ is selected so that it becomes completely charged in approximately five cycles of the input waveform. As already discussed (and illustrated in Fig. 3-37), diode D₁ is forward biased when C₁ is being charged.

Resistor R₁ is not part of the C₁ charging circuit, because D₁ bypasses R₁. As illustrated, C₁ charge is controlled by the signal source resistance (R_S). A capacitor is completely charged in approximately five time constants of the circuit. In the case of a resistor-capacitor circuit, the time constant is RC. So, the charging time is,

When the pulse width and source resistance of the input waveform is known, C₁ can be determined from Eq. 3-44.

So long as the slope on the output waveform is very small, the capacitor discharge current is essentially a constant quantity.

When the output waveform slope is specified, I_C can be calculated from Eq. 3-43, and a suitable resistance for R₁ is then determined by substituting I_C into Eq. 3-45.

Biased Clamping Circuit:

The biased clamping circuit shown in Fig. 3-39 has a bias voltage (V_B) at the cathode of diode D₁.

In this case, the output voltage cannot exceed (V_B1 + V_F), as illustrated. The capacitor charges to (E – V_B1 – V_F) when the input is positive. When the input goes negative, the output voltage is -(E + V_C), giving,

The peak-to-peak output voltage is the difference between the positive and negative output peak levels.

It is seen that, as for other clamping circuits, the peak-to-peak output waveform from the biased damper is the same as the input. The positive level of the output is clamped to (V_B + V_F).

Virtually any bias voltage level (positive or negative) can be used with a biased clamping circuit. The diode polarity determines whether the positive or the negative peak of the output is clamped. Care must be taken to ensure that the capacitor is connected with the correct polarity. Biased clamping circuits are designed in exactly the same way as unbiased clamping circuits.

 Zener Diode Clamping Circuit:

Zener diode clamping circuits operate just like biased voltage dampers, with the Zener diode voltage (V_Z) substituting for the bias voltage.

The circuit in Fig. 3-41 has an ordinary diode (D₁) connected in series with a Zener diode (D₂). When the input voltage is at its positive peak, the output voltage is,

and C₁ charges (+ on the left) to,

When the input goes to its negative peak, the output voltage is,

The peak-to-peak output remains equal to the peak-to-peak input voltage (2E). If the polarity of the diodes (and the capacitor) are reversed, the negative output peak is clamped at -(V_Z + V_F).