Single Stage Common Source Amplifier:

Bias circuit design for the Single Stage Common Source Amplifier in shown in Fig. 12-10. As with the common-emitter BJT circuit, design commences with specification of the supply voltage, amplification, frequency response, load impedance, etc.

Selection of I_D,R_D, and R_s

The circuit shown in Fig. 12-10 has no provision for negative feedback, so, it should be designed to achieve the largest possible gain. The voltage gain of a CS circuit is,

Because A_v is directly proportional to R_D||R_L, design for the greatest voltage gain normally requires selection of the largest possible drain resistance. However, a very large value of R_D might make the drain current too small for satisfactory FET operation. Also, low I_D levels give small Y_fs values, which result in lower ac voltage gain. Furthermore, R_D should normally be much smaller than R_L, so that R_L has little effect on the circuit voltage gain.

For a given level of I_D, the largest possible voltage drop across R_D gives the greatest R_D value, (R_D = V_RD/I_D). To make V_RD as large as possible, V_DS and V_S should be held to a minimum, (see Fig. 12-11(a)]. The drain-source voltage should typically be V_DS(min) = (V_P(max) + 1 V). This is large enough to ensure that the FET operates in the pinch-off region of its characteristics. It also allows for a drain voltage swing of ±1 V, which is usually adequate for a small-signal amplifier. If the gate-source bias voltage (V_GS) is other than zero, then, as illustrated in Fig. 12-11(a), the minimum V_DS should be calculated as,

Recall from earlier article that for good bias stability, the source resistor voltage drop (V_S) should be as large as possible. Where the supply voltage is small, V_S may be reduced to a minimum to allow for the minimum level of V_DS. A reasonable approach for most FET circuits is to calculate the the sum of V_S and V_RD from,

and then make,

Once V_S, V_RD, and I_D are selected, R_D and R_S are calculated,

As already discussed, a bias line should be drawn upon the FET transfer characteristics to determine a suitable gate bias voltage (V_G). The selected maximum drain current (I_D(max)) is plotted on the maximum transfer characteristics for the FET used. The bias line is then drawn through this point with a slope of 1/R_s. The gate bias voltage is read from the intersection of the bias line and the V_G scale. As an alternative to drawing the bias line, V_GS can be read from the transfer characteristic when I_D(max) is plotted. Then,

Instead of using the FET transfer characteristics, V_P(max)  and I_DSS(max) can be substituted to calculate the V_GS level.

Bias Resistors:

With a voltage divider bias circuit [as in Fig. 12-11(13)], R₂ is usually selected as 1 MΩ or less. Smaller resistance values may be used where a lower input impedance is acceptable. Larger resistance values may also be used, however, as discussed earlier, there are distinct disadvantages to using resistances higher than 1 MΩ. With R₂ determined, R₁ is calculated using R₂ and the ratio of V_R1 to V_R2.

Capacitors:

As for a BJT capacitor-coupled circuit, coupling and bypass capacitors should be selected to have the smallest possible capacitance values. The largest capacitor in the circuit (source bypass capacitor C₂ in Fig 12-10) sets the circuit low 3 dB frequency (f₁). Equation 11-10 was developed for the voltage gain of a Single Stage Common Source Amplifier with an unbypassed source resistor (R_S). Rewriting the equation to include X_C2 in parallel with R_S gives

Normally R_S ≫ X_C2, so R_S can be omitted. Also,  X_C2 is capacitive,

When Y_fsX_C2 =1,

Therefore, at f₁,

From Section 11-7,

So, at f₁,

Equations 12-12 gives the smallest value for the source bypass capacitor. When selecting a standard value, the next larger capacitance value should be chosen. This will give a cutoff frequency slightly lower than the f₁ value used in the calculations.

As explained in earlier, it is important to note that the bypass capacitor is calculated in terms of the resistance seen looking into the device terminal (the resistance in series with C₂). The capacitance value is not determined in terms of the parallel resistor (R_S).

The input and output coupling capacitors should have almost zero effect on the circuit frequency response. It is explained that X_C1 in series with Z₁ and X_C3 in series with R_L, constitute voltage dividers that can attenuate the ac input and output voltages. To minimize the attenuation, the reactance of each coupling capacitor is selected to be approximately one-tenth of the impedance in series with it at the lowest operating frequency for the circuit (f₁). Equations 12-4 and 12-5 apply once again for the calculation of the minimum C₁ and C₂ values.

As in BJT circuits, R_L is usually much larger than Z_o, and Z_i is often much larger than r_s, so Z_o and r_s can be omitted in Equations 12-4 and 12-5. As always, the equations give minimum capacitance values, so that the next larger standard values should always be selected for C₁ and C₃.