Capacitor Coupled Class AB Output Stage:

The basic circuit of a Class-AB amplifier using a complementary emitter follower output stage and a Capacitor Coupled Class AB Output Stage load is shown in Fig. 18-18. The circuit is termed a complementary symmetry amplifier. Transistor Q₁ and resistors R₁, R₂, R_C, and R_E1 comprise a common emitter amplifier stage that produces all of the circuit voltage gain. The output of Q₁ is developed across R_C and applied to the bases of Q₂ and Q₃. Capacitor C_o ac couples R_L, and dc isolates R_L to keep it from affecting the circuit bias conditions.

The total voltage drop (V_B) across diodes D₁ and D₂ and resistor R_B forward biases the base-emitter junctions of Q₂ and Q₃ to avoid cross-over distortion. Emitter resistors R_E2 and R_E3 help limit the quiescent current through Q₂ and Q₃. Adjustment of the bias voltage (V_B) is provided by variable resistor R_B. The diodes have voltage drops (V_D) that approximately match the, output transistor V_BE levels. Also, V_D does not change significantly when the diode current changes, so, the diodes behave like bypassed resistors. The diodes and output transistors can be thermally-coupled by mounting D₁ and Q₂ on a single heat sink, and D₂ and Q₃ on a single heat sink. In this case, V_D follows the V_BE level changes with temperature, thus stabilizing the transistor bias conditions over a wide temperature range. The junction of R_E2 and R_E3 must be biased to V_CC/2, so that the output voltage to C_o can swing by equal amounts in positive- and negative-going directions.

Class-AB Capacitor-Coupled Amplifier Design:

Design of the type of circuit shown in Fig. 18-18 is largely a matter of selecting appropriate resistor voltage drops and current levels, and then applying Ohm’s law to calculate the resistor values. The peak output voltage (V_P) and peak output current (I_P) can be determined from earlier Equations, respectively. Those equations were developed for the power delivered to a transformer primary, but they apply equally to power delivered to any load resistor.

The voltage drops across R_E2 and R_E3 when the peak output current is flowing are typically selected as 5% to 10% of the peak output voltage. This is illustrated in Fig. 18-19(a) and (b) where the output capacitor is represented as an ac short-circuit. So,

It should be remembered that R_E2 and R_E3 are included to help stabilize the transistor quiescent currents at a level that eliminates cross-over distortion in the output waveform. For the type of amplifier circuit in Fig. 18-18, without overall negative feedback, it is best to select the emitter resistors as large as possible. Smaller emitter resistors can be used in circuits with dc and ac negative feedback.

When the output is at its negative-going peak, V_CE1 should be 1 V minimum, to ensure that Q₁ does not go into saturation. Also, V_E1 should typically be 3 V. So, the minimum level of V_C1 is typically 4 V, [Fig. 18-19(b)]. Similarly, when the output is at its positive-going peak, there must be an appropriate minimum voltage drop across resistor R_C, [Fig. 18-19(a)]. It is not acceptable to set a 1 V minimum for V_RC, because the current through R_C would be too Small for the required peak base current to Q₂. So, it is best to select,

The minimum current through (I_RC(min)) should typically be selected 1 mA larger than the peak base current for the output transistors. R_C is calculated from V_RC(min) and I_RC(min).

Referring to Fig. 18-19(a), the supply required to produce the positive output peak voltage is

Also, from Fig. 18-19(b), the negative output peak requires,

So, the total supply voltage is,

The voltage drop across the diodes and R_B should just bias Q₂ and Q₃ on for Class-AB operation, (see Fig. 18-20). The current through R_B is the Q₁ quiescent current (I_CQ1), and this is calculated from R_C and the dc voltage drop across R_C. V_RC(dc) equals V_C1(dc), and the sum of them equals (V_CC – V_B), (see Fig. 18-20). So,

The resistance of R_B is now calculated from V_RC(dc) and I_CQ1. Resistors R₁, R₂, and R_E1 are determined in the usual manner for an emitter current bias circuit.

The output transistors should be specified in terms of their maximum voltage, current, and power dissipation. The maximum V_CE for Q₂ and Q₃ (in Fig. 18-18) is the total supply voltage (V_CC). Maximum current for Q₂ and Q₃ is the peak load current plus the selected quiescent current (I_Q23). This normally 1.1 I_p. Transistor power dissipation is calculated by determining the dc power delivered to the output stage from the power supply, and then subtracting the ac load power. The remainder is halved to find the power dissipated in each transistor. Equation 18-12 applies; P_T = 0.5 (P_i – P_o). Recall that the transistors must be operated within the safe operating area of the characteristics.

With a capacitor-coupled load, current is drawn from the power supply during the positive half-cycle of the output, but not during the negative half cycle. The capacitor acts as an energy reservoir to supply load current when the output is negative-going. Consequently, the supply current has a half-wave rectified waveform (see Fig. 18-21), and so,

The dc supply power to the output stage is,

As always, with the exception of the capacitor selected to set the circuit low 3 dB frequency (f₁), each capacitor impedance is selected as one tenth of the impedance in series with the capacitor. Where there is no overall negative feedback, the capacitor with the lowest-value series-connected impedance is normally selected to set f₁. For the circuit shown in Fig. 18-18, the impedance looking into the emitter of Q₁ is h_ib1, and this is in series with C_E. If h_ib1 is smaller than R_L, then at f₁;

Most power amplifiers typically have R_L = 8 Ω or 16 Ω. So, the load-coupling capacitor normally sets the circuit low 3 dB frequency.