CMOS Inverter Working Principle:

CMOS Circuit contain both NMOS and PMOS devices to speed the switching of capacitive loads. It consumes low power and can be operated at high voltages, resulting in improved noise immunity. Fig. 3.1 shows the basic CMOS Inverter Working Principle.

It consists of two MOSFETs in series in such a way that the P-channel device has its source connected to +V_DD (a positive voltage) and the N-channel device has its source connected to ground. The gates of the two devices are connected together as the common input and the drains are connected together as the common output.

When input is HIGH, the gate of Q₁ (P-channel) is at 0V relative to the source of Q₁ i.e. V_GS1 = 0V. Thus, Q₁ is OFF. On the other hand, the gate of Q₂ (N-channel) is at +V_DD relative to its source i.e. V_GS2 = +V_DD. Thus, Q₂ is ON. This will produce V_out ≈ 0 V, as shown in the Fig. 3.2 (a).

When input is LOW, the gate of Q₁ (P-channel) is at a negative potential relative to its source while Q₂ has V_GS = 0 V. Thus, Q₁ is ON and Q₂ is OFF. This produces output voltage approximately +V_DD, as shown in the Fig. 3.2 (b).

Table 3.1 summarizes the operation of CMOS Inverter Truth Table