Common Source JFET Amplifier with AC Equivalent Circuit:

The Common Source JFET Amplifier Circuit configuration is the most widely employed configuration. It is because this configuration provides high input impedance, good voltage gain and moderate output impedance.

The circuit of a common source N-channel JFET amplifier using self bias is shown in Fig. 13.37. The signal source, V_in is connected to JFET gate through coupling capacitor C₁ and external load R_L is connected to the drain terminal D via coupling capacitor C₂. R_G is used to provide leakage path to the gate current, R_S for developing gate bias and C_S for providing ac ground to the input signal.

Note that the polarity of the capacitors in Fig. 13.37—the negative terminal of each (polarized) capacitor must always be at a lower dc potential than the positive terminal. Incorrectly connected capacitors can affect the bias conditions and ac performance of the circuit.

For ac considerations, bypass capacitor C_S effectively ties the FET source terminal to the ground level. Thus, all of the input voltage V_in is developed across the gate source terminals. With the increase or decrease in input voltage, gate-source voltage V_gs changes and corresponding change in V_gs makes the drain current I_D to increase or decrease correspondingly.

The phase relationship between the circuit input and output voltages can be determined by considering the effect of a positive going input signal. When input voltage V_in increases in positive direction, it reduces the negative gate-source voltage, –V_gs. The reduction in –V_gs raises the level of drain current I_D and consequently increases the voltage drop across drain resistance R_D.

Since V_D = V_DD – I_DR_D, the increase in I_D results in a drop in drain (output) voltage V_D. Thus as V_in increases in a positive direction, V_out goes in a negative direction. Similarly when V_in goes negative, the resultant increase in –V_gs reduces the drain current I_D which, in turn, reduces the voltage drop across R_D and develops a positive going output voltage V_out. Thus, the amplifier output voltage is 180° out of phase with the input voltage.

Analysis: The first step in ac analysis of the common source circuit is to draw the ac equivalent circuit. This is done by replacing all the capacitors with short circuits and reducing dc supply voltages to zero. AC equivalent circuit for Common Source JFET Amplifier is given in Fig. 13.38.

Input Resistance: In an ideal JFET R_gs is infinite because I_G = 0. However, in actual device R_gs is not infinite but extremely high (100 MΩ or so) in comparison to R_G. Thus, input resistance

Output Resistance: Looking into the drain and source terminals, the large drain resistance r_d is seen. Thus,

Z_d is the device output impedance; the circuit output impedance is R_D in parallel with Z_d, so

Since usually r_d ≫ R_D, the circuit output impedance is taken to be R_D.

Voltage Gain:

Output voltage,

and voltage gain,

usually r_d ≫ R_D || R_L

So voltage gain,

The minus sign indicates that output voltage V_out is 180° out of phase with input voltage V_in.