DC Load Line of BJT Biasing Circuit:

The DC Load Line of BJT Biasing Circuit is a straight line drawn on the transistor output characteristics. For a common-emitter (CE) circuit, the load line is a graph of collector current (I_C) versus collector-emitter voltage (V_CE), for a given value of collector resistance (R_C) and a given supply voltage (V_CC). The load line shows all corresponding levels of I_C and V_CE that can exist in a particular circuit.

Consider the common-emitter circuit in Fig. 5-1. Note that the polarity of the transistor terminal voltages are such that the base-emitter junction is forward biased and the collector-base junction is reverse biased. These are the normal bias polarities for the transistor junctions. The DC Load Line of BJT Biasing Circuit in Fig. 5-1 is drawn on the device common-emitter characteristics in Fig. 5-2. From Fig. 5-1, the collector-emitter voltage is,

V_CE = (supply voltage) – (voltage drop across R_C)

If the base-emitter voltage (V_BE) is zero, the transistor is not conducting and I_C = 0. Substituting the V_CC and R_C values from Fig. 5-1 into Eq. 5-1,

Plot point A on the common-emitter characteristics in Fig. 5-2 at I_C = 0 and V_CE = 20 V. This is one point on the DC Load Line of BJT Biasing Circuit.

Now assume a collector current of 2 mA, and calculate the corresponding collector-emitter voltage level.

Plot point B on Fig. 5-2 at V_CE = 0 and I_C = 2 mA. The straight line drawn through point A and point B is the dc load line for R_C = 10 kΩ and V_CC = 20 V. If either of these two quantifies is changed, a new load line must be drawn.

As already stated, the DC Load Line of BJT Biasing Circuit represents all corresponding I_C and V_CE levels that can exist in the circuit, as represented by Eq. 5-1. For example, a point plotted at V_CE = 16 V and I_C = 1.5 mA on Fig. 5-2 does not appear on the load line. This combination of voltage and current cannot exist in this particular circuit, (Fig. 5-­1). Knowing any one of I_B, I_C, and V_CE, it is easy to determine the other two from a dc load line drawn on the device characteristics.

It is not always necessary to have the device characteristics in order to draw the DC Load Line of BJT Biasing Circuit. A simple graph of I_C versus V_CE can be used.

DC Bias Point (Q-Point):

The dc bias point, or quiescent point (Q-point) (also known as the dc operating point), identifies the transistor collector current and collector-emitter voltage when there is no input signal at the base terminal. Thus, it defines the dc conditions in the circuit. When a signal is applied to the transistor base, I_B varies according to the instantaneous amplitude of the signal. This causes I_C to vary, and consequently produces a variation in V_CE.

Consider the circuit in Fig. 5-4, and the 10 kΩ load line drawn for the circuit in Fig. 5-5. Assume that the bias conditions are as identified by the Q-point on the load line,

When I_B is increased from 20 μA to 40 μA, I_C becomes approximately 1.95 mA and V_CE becomes 0.5 V, as illustrated at point Con the load line. The V_CE change from the Q-point is,

So, increasing I_B by 20 μA (from 20 μA to 40 μA) caused V_CE to decrease by 9.5 V, (from 10 V to 0.5 V).

Now look at the effect of decreasing the base current. When I_B is reduced from 20 μA to zero, I_C goes down to approximately 0.05 mA, and V_CE goes up to 19.5 V (point D on the load line in Fig. 5-­5). So, the V_CE change is,

Decreasing I_B by 20 μA (From 20 μA to zero) caused V_CE to increase by 9.5 V (from 10 V to 19.5 V). It is seen that with the Q-point at I_C = 1 mA and V_CE = 10 V, an I_B variation of ±20 μA produces a collector voltage swing of ΔV_CE = ±9.5 V.

The base current does not have to be varied by the maximum amounts discussed above; it can be increased and decreased by smaller amounts. For example, a base current change of ±10 μA (from the Q-point on Fig. 5-5) would produce a collector current change of ±0.5 mA, and a collector-emitter voltage change of ±5 V.

The maximum possible transistor collector-emitter voltage swing for a given circuit can be determined without using the transistor characteristics. For convenience, it may be assumed that I_C can be driven to zero at one extreme and to V_CC/R_C at the other extreme, [see Fig. 5-6]. This changes the collector-emitter voltage from V_CE = V_CC  to V_CE = 0, as illustrated in Fig. 5-7. Thus, with the Q-point at the center of the load line, the maximum possible collector voltage swing is seen to be approximately ±V_CC/2

Q-point Selection:

Suppose that, instead of being biased half way along the load line, the transistor is biased at I_C = 0.5 mA, and V_CE = 15 V, as shown in Fig. 5-8(a). Increasing the collector current to 2 mA reduces V_CE to zero, giving ΔV_CE = -15 V. Reducing I_C to zero increases V_CE to V_CC, producing ΔV_CE = +5 V.

When used as an amplifier, the transistor output (collector-emitter) voltage must swing up and down by equal amounts; that is, the output voltage swing must be symmetrical above and below the bias point. So, the asymmetrical V_CE swing of -15 V +5 V illustrated in Fig. 5-8(a) is unsuitable. If I_C is driven up and down by ±0.5 mA [see Fig. 5-8(b)], a symmetrical output voltage swing of ±5 V is obtained. This is the maximum symmetrical output voltage swing that can be achieved with the bias point shown in Fig. 5-8.

In many cases circuits are designed to have the Q-point at the center of the load line (as in Figs. 5-5 and 5-7) to give the largest possible symmetrical output voltage swing. This is especially true for some large signal amplifiers. Small signal amplifiers usually require an output voltage swing not greater than ±1 V. So,

Transistors in amplifiers do not all have to be biased at the center of the dc load line.

Effect of Emitter Resistor:

Figure 5-11(a) shows a circuit that has a resistor (R_E) in series with the transistor emitter terminal, and the supply voltage connected directly to the collector terminal. In this case R_E is the dc load, and Eq. 5-1 is rewritten as,

The DC Load Line of BJT Biasing Circuit is drawn exactly as discussed, with I_E taken as equal to I_C for convenience.

In Fig. 5-11(b) collector and emitter resistors R_C and R_E are both present, and the total dc load in series with the transistor is (R_C+ R_E). For drawing the DC Load Line of BJT Biasing Circuit, Eq. 5-1 is modified to,

Note that the voltage drop across the emitter resistor is actually (I_E R_E), but again for convenience I_E is taken as equal to I_C.