FET Biasing Methods – Fixed Bias, Self Bias, Potential Divider Bias and Current Source Bias:

Unlike BJTs, thermal runaway does not occur with FETs. However, the wide differences in maximum and minimum transfer characteristics make I_D levels unpredictable with simple fixed-gate bias voltage. To obtain reasonable limits on quiescent drain currents I_D and drain-source voltage V_DS, source resistor and potential divider bias techniques must be used. With few exceptions, MOSFET bias circuits are similar to those used for JFETs. Various FET Biasing Methods are discussed below :

Fixed Bias:

In this FET Biasing Methods, DC bias of a FET device needs setting of gate-source voltage V_GS to give desired drain current I_D. For a JFET drain current is limited by the drain-source saturation current I_DSS. Since the FET has such a high input impedance that no gate current flows and the dc voltage of the gate set by a voltage divider or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias is obtained using a battery V_GG. This battery ensures that the gate is always negative w.r.t. source and no current flows through resistor R_G and gate terminal i.e. I_G ≡ 0. The battery provides a voltage V_GS to bias the N-channel JFET, but no resulting current is drawn from the battery V_GG. Resistor R_G is included to allow any ac signal applied through capacitor C to develop across R_G. While any ac signal will develop across R_G, the dc voltage drop across R_G is equal to I_GR_G i.e. 0 volt.

The gate-source voltage V_GS is then

The drain-source current I_D is then fixed by the gate-source voltage.

This current then causes a voltage drop across the drain resistor R_D and is given as

and output voltage,

Since V_GG is fixed value of dc supply and the magnitude of gate-to-source voltage V_GS is also fixed, hence this circuit is named as fixed bias circuit. Since this bias circuit uses two batteries V_DD and V_GG, it is also known as two battery bias circuit.

A FET has a high input impedance. To make advantage of it, R_G should be as large as possible so that the input impedance of the circuit remains high. If R_G is extremely large a charge accumulated on the gate may take a long time to leak off. A reasonable upper limit is 1 MΩ. Normally R_G should not exceed this value.

Self-Bias:

This is the most common FET Biasing Methods. Self-bias for an N-channel JFET is shown in Fig. 13.15. This circuit eliminates the requirement of two dc supplies i.e., only drain supply is used and no gate supply is connected. In this circuit, a resistor R_S, known as bias resistor, is connected in the source leg.

The dc component of drain current I_D flowing through R_S makes a voltage drop across resistor R_S. The voltage drop across R_S reduces the gate-to-source reverse voltage required for FET operation. The capacitor C_S bypasses the ac component of the drain current I_D. The addition of resistor R_G in the circuit does not disturb the dc bias. This is because gate current flowing through it is zero and the gate leakage current is also almost zero.

Thus, gate is essentially at dc ground. The resistor R_G is inserted in the circuit to avoid the short circuiting of the ac input voltage. Further, if there is a leakage, the resistor R_G will provide to it an escape route. Otherwise, the leakage current would build up static charge (voltage) at the gate which could change the bias. The resistor R_S, the feedback resistor, also helps in preventing any variation in FET drain current.

Since no gate current flows through the reverse-biased gate, the gate current I_G = 0 and, therefore,

With a drain current I_D the voltage at the S is

The gate-to-source voltage is then

So voltage drop across resistance R_S provides the biasing voltage V_GS and no external source is required for biasing and this is the reason that it is called self-biasing.

The operating point (i.e. zero signal I_D and V_DS) can easily be determined and equation given below :

Thus dc conditions of JFET amplifier are fully specified.

Self-biasing of a JFET stabilizes its quiescent operating point against any change in its parameters like transconductance. Let the given JFET be replaced by another JFET having the double conductance then drain current will also try to be double but since any increase in voltage drop across R_S, therefore, gate-source voltage, V_GS becomes more negative and thus increase in drain current is reduced.

Potential Divider Bias:

A slightly modified form of DC FET Biasing Methods is provided by the circuit shown in Fig. 13.16. The resistors R_G1 and R_G2 form a potential divider across drain supply V_DD. The voltage V₂ across R_G2 provides the necessary bias. The additional gate resistor R_G1 from gate to supply voltage facilitates in larger adjustment of the dc bias point and permits use of larger valued R_S.

The gate is reverse biased so that I_G = 0 and gate voltage

The circuit is so designed that I_DR_S is larger than V_G (or V₂) so that V_GS is negative. This provides correct bias voltage.

The operating point can be determined as

Maximum gain is achieved by making resistance R_D as large as possible and for a given level of I_D it needs maximum voltage drop across resistor R_D. However, greatest bias stability is achieved by making R_S as large as possible.

If the gate voltage V_G is very large as compared to gate-to­-source voltage V_GS, the drain current is approximately constant. In practice, the voltage divider bias is less effective with JFET than BJT. This is because in BJT, V_BE = 0.7 V (silicon) with only minor variations from one transistor to another transistor. But in a JFET, the V_GS can vary several volts from one JFET to another.

Current-Source Bias:

In this FET Biasing Methods, When the drain supply voltage V_DD is not large, there may not be enough gate voltage to swamp out the variations in V_GS. In such a case current-source bias (Fig. 13.17) may be used. In this arrangement, the BJT pumps a fixed current through the JFET. The drain current is given by

Figure 13.18 illustrates how effective current-source bias is. Both Q points have the same value of drain current. Although V_GS is different for each Q point, V_GS no longer has any effect on the value of drain current.