JFET Biasing Circuits:

Use of Plus/Minus Supplies – When plus/minus supply voltages are to be used with a JFET Biasing Circuits, the gate terminal is usually grounded via R_G, as illustrated in Fig. 10-40(a). In this case, the circuit is essentially a voltage divider bias circuit with the gate bias voltage equal to the level of the negative supply voltage, (V_G = V_SS). The (reverse) gate-source bias voltage (-V_GS) makes the source terminal +V_GS above ground. So, 

When the voltage levels are understood, the type of circuit in Fig. 10-40(a) can be designed using a procedure similar to that for a voltage divider bias circuit. I_D(max) is plotted on the maximum transfer characteristics, and V_GS is read from the horizontal axis V_GS can also be determined by substituting I_D(max), I_DSS(max), and V_P(max) into Eq. 10-8. Then, with the desired maximum voltage drops known, R_D and R_S are readily calculated. R_G is selected as 1 MΩ, or less, for the reasons already discussed.

Analysis procedure for this circuit is also like that for a voltage divider bias circuit. One point on the bias line is plotted on the transfer characteristics at V_G = V_SS, as shown on Fig. 10-40(b), and the bias line is drawn at the slope determined by R_s. As always, the bias line intersections with the maximum and minimum characteristics gives the I_D(max) and I_D(min) levels.

Drain Feedback:

The drain feedback JFET Biasing Circuits in Fig. 10-41 is essentially a voltage divider bias circuit. However, instead of V_G being derived from the supply voltage, the FET drain voltage (V_D) is divided by R₁ and R₂ to produce V_G. Modifying Eq. 10-7,

The circuit is designed for a particular level of V_D and I_D, and the voltage drop across R_S helps to stabilize I_D, as in other voltage divider bias circuits. The voltage drop across R_D also provides feedback that helps to correct changes in I_D. When I_D is greater than the design value, V_RD is increased, V_D is reduced, and thus V_G is lowered to drive I_D back toward its original level. The two feedback effects (V_RD changes and V_RS changes) tend to keep I_D(min) and I_D(max) closer than in an ordinary voltage divider JFET Biasing Circuits.

Design procedure for this circuit is the same as for voltage divider bias with the exception that the voltage drop across R₁ is (V_D – V_G) instead of (V_DD – V_G). For circuit analysis a bias line should be drawn on the transfer characteristics, as always. This requires the equation relating V_GS and I_D.

Constant Current Bias:

As already discussed, the bias lines with the smallest slope give the closest levels of I_D(min) and I_D(max). In the two circuits in Fig. 10-42 the bipolar transistor (Q₂) keeps the FET source current constant. Consequently, as illustrated in Fig. 10-43, the bias line is drawn horizontally on the transfer characteristics, showing I_D(min) = I_D(max), with different V_GS levels.

Both circuits provide bias voltage V_B to the base of Q₂, to give,

The circuit in Fig. 10-42(a) uses voltage divider bias to derive V_B from V_DD, and in Fig. 10-42(b) V_B = V_EE. In both cases, the FET gate is connected to the base of Q₂ via resistor R_G, and V_GS = -V_CB.

Design of each of the circuit in Fig. 10-42 simply involves selection of appropriate voltage and current levels and calculation of the resistors. The emitter resistor voltage drop (V_E) should typically be a minimum of 5 V, but satisfactory results can be obtained with 3 V. It can, of course, be much larger than 5 V, as would normally be the case in Fig. 10-42(b). In both circuits,

The level of V_B calculated in this way can be used to determine the ratio of R₁ and R₂ in Fig. 10-42(a). For the circuit in Fig. 10-42(b), V_EE indicates the V_B and V_E levels.

The maximum V_GS level is determined by plotting I_D on the maximum transfer characteristic for the FET, and then reading V_GS(max) at I_D. Alternatively, V_GS can be calculated from Eq. 10-8. The source terminal voltage is more positive than the gate. The equation for V_S,

Analysis of each of the circuits in Fig. 10-42 is very simple. Once V_B is determined, I_D is calculated using Eq. 10-17. V_GS(max) and V_GS(min) are found by drawing the bias line for I_D on the transfer characteristics, or by substituting I_D, V_P, and I_DSS into Eq. 10-8.