JFET Characteristics:

An n-channel JFET Characteristics block representation is shown in Fig. 9-6. With a drain-source voltage applied as illustrated, I_D flows in the direction shown producing voltage drops along the channel. Consider the voltage drops from the source terminal (S) to points A, B. and C within the channel. Point A is positive with respect to the source: alternatively, it can be stated that S is negative with respect to A. Because the gate blocks are connected to S, the gates are negative with respect to point A by a voltage V_A. This causes the depletion regions to penetrate into the channel by an amount proportional to V_A.

The voltage drop between point B and the source is V_B, which is less than V_A. Consequently, at point B on the channel the gates are at -V_B with respect to the channel, and the depletion region penetration is less than at point A. From point C to the source terminal, the voltage drop (V_C) is less than V_B. Thus, the gate-channel reverse bias (at point C) is V_C volts, and the depletion region penetration is less than at point A or B. The differing voltage drops along the channel, and the resulting variation in gate-channel reverse bias, accounts for the shape of the depletion region penetration of the channel.

Drain Characteristics of jfet with V_G = 0:

Figure 9-7 shows a circuit for determining the drain current versus drain-source voltage characteristics of n channel jfet with V_GS = 0. V_DS is increased in convenient steps from zero, and I_D is measured at each V_DS level. This produces a table of I_D/V_DS values for plotting the characteristic shown in Fig. 9-8.

Referring to the JFET Characteristics, it is seen that when V_DS = 0, I_D = 0. There is no channel voltage drop, so the voltage between the gate and all points on the channel is zero, and there is no depletion region penetration. When V_DS is increased by a small amount (less than 1 V), a small drain current flows producing some voltage drop along the channel. This results in some depletion penetration of the channel (as explained for Fig. 9-6), but it is so small that it has no significant effect on the channel resistance. With further small increases in V_DS the drain current increase is approximately linear, and the channel behaves as an almost constant-value resistance, (see Fig. 9-8).

The channel continues to behave as a fixed-value resistance until the voltage drops along it become large enough to produce considerable depletion region penetration. At this stage the channel resistance begins to be affected by the depletion regions. Further increases in V_DS now produce smaller I_D increases, as shown by the curved part of the JFET Characteristics. The increased I_D levels, in turn, cause more depletion region penetration and greater channel resistance. Eventually, a saturation level of I_D is reached where further V_DS increase seems to have no effect on I_D.

At the point on the characteristic where I_D levels off, the drain current is referred to as the drain-source saturation current(I_DSS). (10 mA in Fig. 9-8). The shape of the depletion regions in the channel at the I_DSS level is such that they appear to pinch off the channel, (see Fig. 9-6). So, the drain source voltage at this point is termed the pinch-off voltage (V_P), (4.5 V in Fig. 9-8.) The region of the JFET Characteristics where I_D is constant is called the pinch-off region, as illustrated. The channel mostly behaves like a resistance between V_DS = 0 and V_DS = V_P, so this part of the characteristic is referred to as the channel ohmic region.

If V_DS is continuously increased (in the pinch-off region) a voltage is reached at which the (reverse-biased) gate-channel junctions break down, (see Fig. 9-8). When this occurs, I_D increases rapidly, and the device might be destroyed. The pinch-off region of the characteristic is the normal operating region for the FET.

Drain Characteristics with External Bias:

A circuit for obtaining the I_D/V_DS characteristics for an n-channel JFET when an external gate-source bias (V_GS) is applied is shown in Fig. 9-9. In this case, V_GS is set to a convenient (negative) level (such as -1 V). V_DS is increased in steps, and the corresponding level of I_D is noted at each V_DS step. The I_D/V_DS characteristic for V_GS = -1 V is then plotted as illustrated in Fig. 9-10.

When a -1 V external gate-source bias voltage is applied, the gate-channel junctions are reverse biased even when I_D = 0. So, when V_DS = 0 the depletion regions are already penetrating to some depth into the channel. Because of this, a smaller voltage drop along the channel (smaller than when V_GS = 0) will increase the depletion regions to the point at which they produce channel pinch-off. Consequently, with V_GS = -1 V the pinch-off voltage is reached at a lower I_D level than when V_GS = 0. The V_GS = -1 V characteristic In Fig. 9-10 has V _p = 3.5 V.

A family of drain characteristics can be obtained by using several levels of negative gate-source bias voltage, (see Fig. 9-11). If a positive V_GS is used, a higher level of I_D can be produced, as shown by the JFET Characteristics for V_GS = +0.5 V. However, V_GS is normally kept negative to avoid the possibility of forward biasing the gate-channel junctions.

The dashed line on the characteristics in Fig. 9-11 is drawn through the points at which I_D saturates for each level of gate-source bias voltage. When V_GS = 0, I_D saturates at I_DSS, and the characteristic shows V_P = 4.5 V. When a -1 V external bias is applied, the gate-channel junctions still require -4.5 V to achieve pinch-off, This means that a 3.5 V drop is now required along the channel instead of 4.5 V, and the lower voltage drop is achieved with a lower level of I_D. Similarly, when V_GS = -2 V and – 3 V, pinch-off is achieved with 2.5 V and 1.5 V, respectively, along the channel. The 2.5 V and 1.5 V drops are, of course, obtained with further reduced I_D levels.

Suppose a -4.5 V gate-source bias is applied to a device with the JFET Characteristics shown in Fig. 9-11. This is a V_GS level equal to the pinch-off voltage V_p. Without any additional channel voltage drop produced by I_D, the depletion regions penetrate so deep into the channel that they meet in the middle, completely cutting I_D off.  So, a gate-source bias equal to the pinch-off voltage reduces I_D to zero. The bias voltage required to do this is termed the gate cutoff voltage (V_GS(0)). and, as explained. V_GS(0) = V_p. Note on Fig. 9-11 that the drain-source voltage at which breakdown occurs is reduced as the negative gate-source bias voltage is increased. This is because -V_GS adds to the reverse bias at the junctions.

Transfer Characteristics of jfet:

Transfer Characteristics of jfet are a plot of I_D versus V_GS. The gate-source voltage of a FET controls the level of the drain current, so, the transfer characteristic shows how I_D is controlled by V_GS. As illustrated in Fig. 9-13(a), the transfer characteristic extends from I_D = I_DSS at V_GS = 0, to I_D = 0 at V_GS = V_p.

Figure 9-13(b) shows a circuit for experimentally determining a table of quantities for plotting the transfer characteristic of a given FET. The drain-source voltage is maintained constant, V_GS is adjusted in convenient step, and the corresponding levels of V_GS and I_D are recorded. The characteristic shows that, as -V_GS is increased, I_D is progressively reduced from I_DSS at V_GS = 0, to I_D = 0 at V_GS = -V_p

The transfer characteristic for a FET can be derived from the drain characteristics. A line is drawn vertically on the drain characteristics to represent a constant V_DS level. The corresponding I_D and V_GS values along this line are noted and then used to plot the transfer characteristic.

p channel jfet characteristics:

Figure 9-15 shows a circuit for obtaining the JFET Characteristics of a p-channel JFET. Note the direction of the arrowhead on the PET symbol, and the drain current direction. Also, note the supply voltage polarity, and the polarity of the gate-source bias voltage. The drain terminal is negative with respect to the source, and the gate terminal is positive with respect to the source. To obtain a table of quantities to plot a drain characteristic, V_GS is maintained constant at the desired (positive) level, -V_DS is increased in steps from zero, and the I_D levels are noted at each step.

Typical p- hannel JFET drain characteristics and transfer characteristics are shown in Fig. 9-16. It is seen that these are similar to the characteristics for an n-channel JFET, except for the voltage polarities. In Fig. 9-16, when V_GS = 0, I_DSS = 15 mA, and progressively more positive levels of V_GS reduce the level of I_D toward cutoff at V_p = +6 V. Using V_GS = -0.5 V produces a higher level of I_D than when V_GS = 0. As in the case of the n-channel JFET, forward bias at the gate-channel junctions should be avoided, consequently, negative V_GS levels are normally not used with a p-channel JFET.

The transfer characteristics of p channel jfet device can be obtained experimentally, or can be derived from the drain characteristics, just as for an n-channel FET.