Gate Bias Circuit

Gate Bias Circuit: Circuit Operation - Consider the Gate Bias Circuit shown in Fig. 10-6. The FET gate terminal is connected via resistor RG to a bias voltage VG. If…

Continue Reading Gate Bias Circuit

Emitter Bias Circuit Diagram

Emitter Bias Circuit Diagram: This Emitter Bias Circuit Diagram is obtained by simply introducing an emitter resistor to the fixed bias circuit as shown in Fig. 12.9. For analysis, we…

Continue Reading Emitter Bias Circuit Diagram

Performance of CMOS Gates

Performance of CMOS Gates: The Performance of CMOS Gates which based on following different categories namely, Operating Speed : Slower than TTL series. Approximately 25 to 100 ns depending on…

Continue Reading Performance of CMOS Gates

FET Biasing Articles

FET Biasing Articles: DC Load Line for FET: The DC Load Line for FET circuit is drawn on the device output characteristics (or drain characteristics) in exactly the same way…

Continue Reading FET Biasing Articles

Biasing Bipolar Op Amp Circuit

Biasing Bipolar Op Amp Circuit: Biasing Bipolar Op Amp Circuit - Like other electronic devices, operational amplifiers must be correctly biased if they are to function properly. As already discussed,…

Continue Reading Biasing Bipolar Op Amp Circuit

Common Gate Circuit

Common Gate Circuit: The FET Common Gate Circuit (CG) shown in Fig. 11-19 uses voltage divider bias. The ac output is taken from the drain terminal, and an external load…

Continue Reading Common Gate Circuit