Power Supply Source Effect in Semiconductor:

Power Supply Source Effect in Semiconductor shows that the ac supply to the input of a transformer in a dc power supply does not always remain constant. A ±10% variation in the ac source voltage (V_S) (also termed the line voltage) is not unusual.

When the source voltage varies, there is some variation in the dc output voltage from a power supply, (see Fig. 3-18). This output voltage change (ΔE_o) due to a change in the input is termed the source effect.

If the output varies by 100 mV when the source voltage changes by ±10%, the source effect is 100 mV.

An alternative way of stating this output change is to express ΔE_o as a percentage of the dc output voltage (E_o). In this case, the term line regulation is used.

Load Effect:

Power supply output voltage is also affected by changes in load current (I_L). The output voltage decreases when I_L is increased, and rises when I_L is reduced.

The load effect defines how the output voltage changes when the load current is increased from zero to its specified maximum level (I_L(max)). If the load current change (ΔI_L) produces a voltage change (ΔE_o) of 100 mV, the load effect is 100 mV.

As for the source effect, the load effect can also be expressed as a percentage of the output voltage. This is termed the load regulation.