8259 Programmable Interrupt Controller

8259 Programmable Interrupt Controller:

The 8259 Programmable Interrupt Controller requires two types of command words. Initialization Command Words (ICWs) and Operational Command Words (OCWs). The 8259 Programmable Interrupt Controller can be initialized with four ICWs; the first two are compulsory, and the other two are optional based on the modes being used. These words must be issued in a given sequence. After initialization, the 8259A can be set up to operate in various modes by using three different OCWs; however, they are not necessary to be issued in a specific sequence. Refer Fig. 14.75 for initialization flowchart.

Initialization Command Word 1 (ICW1):

Fig. 14.76 shows the Initialization Command Word 1(ICW1). A write command issued to the 8259 with A₀ = 0 and D₄ = 1 is interpreted as ICW1, which starts the initialization sequence. It specifies,

Single or multiple 8259As in the system
4 or 8 bit interval between the interrupt vector locations.
The address bits A₇ – A₅ of the CALL instruction. (3 bits of lower byte address of CALL are given by user, rest bits are inserted by 8259A)
Edge triggered or level triggered interrupts.
ICW4 is needed or not.

Initialization Command Word 2 (ICW2):

Fig. 14.77 shows the Initialization command Word 2 (ICW2).

A write command following ICW1, with A₀ = 1 is interpreted as ICW2. This is used to load the high order byte of the interrupt vector address of all the interrupts.

Initialization Command Word 3 (ICW3):

ICW3 is required only if there is more than one 8259 in the system and if they are cascaded. An ICW3 operation loads a slave register in the 8259 Programmable Interrupt Controller. The format of the byte to be loaded as an ICW3 for a master 8259 or a slave is shown in the Fig. 14.78. For master, each bit in ICW3 is used to specify whether it has a slave 8259 attached to it on its corresponding IR (Interrupt Request) input. For slave, bits D₀ – D₂ of ICW3 are used to assign a slave identification code (slave ID) to the 8259 Programmable Interrupt Controller.

Initialization Command Word 4 (ICW4):

It is loaded only, if the D₀ bit of ICW1 is seta The format of ICW4 is shown in Fig. 14.79.

It specifies,

Whether to use special fully nested mode or non special fully nested mode.
Whether to use buffered mode or non buffered mode.
Whether to use Automatic EOI or Normal EOI.
CPU used, 8086/8088 or 8085.

Operation Command Words (OCWs):

After initialization, the 8259 Programmable Interrupt Controller is ready to process interrupt requests. However, during operation, it might be necessary to change the mode of processing the interrupts. Operation Command Words (OCWs) are used for this purpose. They may be loaded anytime after the initialization of 8259 to dynamically alter the priority modes.

Operation Command Word 1 (OCW 1):

A Write command to the 8259 with A₀ = 1 (after ICW2) is interpreted as OCW1. OCW1 is used for enabling or disabling the recognition of specific interrupt requests by programming the IMR.

M = 1 indicates that the interrupt is to be masked, and M = 0 indicates that it is to be unmasked as shown in Fig. 14.80.

Operation Command Word 2 (OCW2):

A Write command with A₀ = 1 and D₄ D₃ = 00 is interpreted as OCW2. The R (Rotate), SL (Select-Level), EOI bits control the Rotate and End Of Interrupt Modes and combinations of the two. Fig. 14.81 shows the Operation Command Word format. L₂-L₀ are used to specify the interrupt level to be acted upon when the SL bit is active.

Operation Command Word 3 (OCW3):

OCW3 is used to read the status of the registers; and to set or reset the Special Mask and Polled modes. Fig. 14.82 shows format of operation command word 3.

8259 Status Read Operations:

The status of the Interrupt Request Register, the Interrupt-Service Register, and the Interrupt Mask Regiter of the 8259 may be read by issuing appropriate Read commands as described further.

IRR Status Read:

An OCW3 with RR (Read Register) = 1 and RIS (Read ISR) = 0 set up the 8259 for a status read of the Interrupt Request Register.

When the 8259 is not in the Polled mode, after it is set up for. an IRR status read operation, all Read commands with A₀=1 cause the 8259 to send the IRR status word.

ISR Status Read:

An OCW3 with RR = 1 and ISR = 1 sets up the 8259 for a status read of the Interrupt-Service Register. A subsequent read command issued to the 8259 will cause the 8259 to send the contents of the ISR onto the data bus.

IMR Status Read:

A Read command issued to the 8259 Programmable Interrupt Controller with A₀ = 1 (with RD, CS = 0 ) causes the 8259 to put the contents of the Interrupt Mask Register on the data bus. OCW3 is not required for a status read of the IMR.

As described earlier, the sequence shown in flowchart must be followed to initialize 8259A. According to this flow chart, an ICW1 and an ICW2 must be sent to any 8259A in the system. If the system has any slave 8259As (cascade mode), then an ICW3 must be sent to the master, and a different ICW3 must be sent to the slave. If the system is an 8086, or if you want to specify certain special conditions; then you have to send an ICW4 to the master and to each slave.