Self Bias Circuit Diagram:

Circuit Operation – In a self bias JFET circuit, gate-source bias is provided by the voltage drop across a resistor in series with the device source terminal. Consider the n-channel JFET Self Bias Circuit Diagram illustrated in Fig. 10-11. The voltage drop across resistor R_S is,

 

If I_D = 1 mA and R_S = 1 kΩ, then V_S =1 V. This means that, the source terminal in Fig. 10-11 is 1 V positive with respect to ground. Alternatively, ground can be said to be 1 V negative with respect to the source terminal. Because the FET gate terminal is grounded via R_G (and there is no voltage drop across R_G), the gate is 1 V negative with respect to the source. That is, the gate-source bias voltage is V_GS = -1 V. So, for a Self Bias Circuit Diagram,

The fact that I_D determines V_GS, and that V_GS sets the I_D level, means that there is a feedback effect tending to control I_D. Thus, if I_D increases when the device is changed, the increased voltage across R_S results in an increased (negative) gate-source voltage that tends to reduce I_D back toward its original level. Similarly, a fall in I_D produces a reduced V_GS which tends to increase I_D toward its original level.

Circuit Analysis:

As for all FET bias circuits, a graphical technique is most convenient for analysis of a Self Bias Circuit Diagram. In this case, the bias line drawn on the transfer characteristics is quite different from that for the gate bias circuit. The value of R_S and convenient I_D levels are inserted into Eq. 10-4 to determine corresponding V_GS levels. The I_D and V_GS values are plotted on the transfer characteristics, and the bias line is drawn through them, (see Fig 10-12). The intersection points of the bias line and the transfer characteristics gives the maximum and minimum I_D levels.

Summing the voltage drops across R_D, R_S, and the FET drain-source terminals in Fig. 10-11 gives,

Equation 10-5 may be used to calculate the maximum and minimum levels of V_DS when I_D(max) and I_D(min) have been determined.

Self-Bias for a p-channel JFET:

A Self Bias Circuit Diagram using a p-channel JFET is shown in Fig. 10­-16. The gate-source bias voltage is once again provided by the voltage drop across source resistor R_S. In this case, the source is negative with respect to the supply voltage (+V_DD). Because the gate is connected to +V_DD via R_G, the gate is is positive with respect to the source terminal. The positive level of V_GS provides the reverse bias at the gate-channel junctions of the p-channel FET. A p-channel Self Bias Circuit Diagram can be analyzed in exactly the same way as an n-channel circuit.