Universal Transfer Characteristics for FET:

A Universal Transfer Characteristics for FET is simply a transfer characteristic plotted with I_DSS = 1 and V_P = 1. Then, instead of the scales being calibrated in milliamps and volts, they are marked as the ratios I_D/I_DSS and V_GS/V_P. To construct the Universal Transfer Characteristics for FET, Eq. 9-1 is rewritten,

Now, by substituting convenient values for V_GS/V_P into Eq. 10-18 corresponding values of I_D/I_DSS are calculated, and these are used to plot the characteristic shown in Fig. 10-45.

The Universal Transfer Characteristics for FET can be applied to analyze or design a circuit using virtually any JFET. This saves the necessity of plotting the transfer characteristics for each device. The specified values of I_Dss and V_p must be known for the device. Then, the characteristic is used in the same way as an actual transfer characteristic, except that V_GS levels must be converted to V_GS/V_P ratios, and I_D levels must be converted to I_D/I_DSS before they can be plotted on the graph. Similarly, readings taken from the graph are converted back to V_GS and I_D levels by multiplying them by V_p and I_Dss respectively.

Circuit Analysis:

Consider the gate bias circuit analyzed in already, and reproduced in Fig. 10-46. The gate voltage is given as -2.3 V, and the device used has I_DSS(max) =  8 mA and V_P(max) = -6 V. The bias line is drawn vertically on the Universal Transfer Characteristics for FET at,

The gate bias line drawn (at V_GS/V_p = 0.38) on Fig. 10-45 intersects the universal characteristic at the point where I_D/I_DSS = 0.375,

This is the I_D(max) level.

The minimum I_D for a gate bias circuit can be determined from the Universal Transfer Characteristics for FET, by using the I_DSS(min) and V_P(min) values. Bias lines can also be drawn for analysis of self bias circuits and voltage divider bias circuits.