Voltage Doubler Circuit:

A Voltage Doubler Circuit produces an output voltage which is approximately double the peak voltage of the input waveform. Consideration of the voltage doubler circuit diagram in Fig. 3-42 shows that it is simply a combination of two diode-capacitor clamping circuits without the discharge resistors. In fact, the circuit operation is similar to that of clamping circuits.

When the input voltage is negative, as shown in Fig. 3-43(a), diode D₁ is forward biased, and C₁ charges to (E – V_F1) with the polarity illustrated. D₂ is reverse biased during the negative half-cycle of the input, so the charge on C₂ Is not affected at this time.

Figure 3-43(b) shows what occurs during the input positive half-cycle. D₁ is now reverse biased, and D₂ is forward biased. The voltage applied to D₂ and C₂ is the sum of the input voltage and the voltage on C₁. So, as illustrated, capacitor C₂ is charged to,

It is seen that, when the diode voltage drop is much smaller than the input voltage, the output is approximately double the peak input amplitude. The polarity of the output voltage can be reversed by reversing the polarity of the diodes and capacitors.

The output terminals of the Voltage Doubler Circuit are the terminals of capacitor C₂. The load current partially discharges the capacitors, producing an output voltage drop in the same way that tilt is created on a clamping circuit output. The repeated charge and discharge of C₁ and C₂ results in a ripple waveform on the output.

A sinusoidal input waveform to a Voltage Doubler Circuit produces exactly the same type of output ripple that occurs with a half-wave rectifier, [Fig. 3-44(a)]. However, the input most often used is a dc voltage source which has been chopped, or converted into a square waveform, [Fig. 3-44(b)].

Capacitor C₂ supplies the load current (I_L) while diode D₂ is reverse biased, [Fig. 3-45(a)]. The discharge of C₂ accounts for half the output ripple voltage amplitude, and the discharge of C₁ produces the other half of the ripple amplitude. Equation 3-43 can be modified for calculating the capacitance of C₂.

While D₂ is forward biased [Fig. 3-45(b)], capacitor C₁ supplies I_L and the recharging current to C₂. The recharging current must equal I_L to maintain the full charge on C₂, so C₁ supplies 2I_L. Applying Eq. 3-43 to calculate C₁, it is found that,

Four Stage DC Voltage Multiplier Circuit:

A Four Stage DC Voltage Multiplier Circuit is shown in Fig. 3-47. Comparing to the voltage doubler in Fig. 3-42, it is seen that this circuit consists of two cascade-connected voltage doubling circuits. To simplify the explanation of the circuit operation, assume ideal diodes with V_F = 0.

• When V_i = -E; D₁ is forward biased, and C₁ charges via D₁ to E.
• When V_i = +E; point A is at +2E, D₁ is reverse biased, D₂ is forward biased, C₂ charges via D₂ to 2E.
• When V_i = -E; point A is close to ground level, point B is at 2E (because of V_C2), D₂ is reverse biased, D₃ is forward biased, and C₃ charges via D₃ to 2E volts.
• When V_i= +E; point A is at +2E, point B is at +2E, and point C is at +4E, D₄ is forward biased, and C₄ charges via D₄ to 2E volts.

The resulting output voltage, taken across C₂ and C₄ is 4E volts, as illustrated. Additional stages may be added to the circuit to produce higher levels of dc output voltage. Figure 3-48 shows another way that do DC Voltage Multiplier Circuit diagrams are often drawn. Examination of the circuit shows that it is exactly the same as Fig. 3-47.