Voltage Multiplier Circuits:

Cascaded Voltage Multiplier Circuits for higher voltages are cumbersome and require too many supply and isolating transformers. It is possible to generate very high d.c. voltages from single supply transformers by extending the simple voltage doubler circuits. This is simple and compact when the load current requirement is less than one milliampere, such as for cathode ray tubes, etc. Valve type pulses generators may be used instead of conventional a.c. supply and the circuit becomes compact. A typical circuit of this form is shown in Fig. 6.4a.

The pulses generated in the anode circuit of the valve P are rectified and the voltage is cascaded to give an output of 2nV_max across the load R_L. A trigger voltage pulse of triangular waveform (ramp) is given to make the valve switched on and off. Thus a voltage across the coil L is produced and is equal to V_max = I√L/C_P, where C_P is the stray capacitance across the coil of inductance L. A d.c. power supply of about 500 V applied to the pulse generator, is sufficient to generate a high voltage d.c. of 50 to 100 kV with suitable number of stages.

The pulse frequency is high (about 500 to 1000 Hz) and the ripple is quite low (<1%). The voltage drop on load is about 5% for load currents of about 150 μA. The voltage drops rapidly at high load currents.

Voltage Multiplier Circuits using the Cockcroft-Walton principle is shown in Fig. 6.4b. The first stage, i.e. D₁,D₂,C₁,C₂, and the transformer T are identical as in the voltage doubler shown in Fig. 6.3. For higher output voltage of 4, 6, … 2n of the input voltage V, the Voltage Multiplier Circuits is repeated with cascade or series connection. Thus, the capacitor C₄ is charged to 4V_max and C_2n to 2nV_max above the earth potential. But the voltage across any individual capacitor or rectifier is only 2V_max.

The rectifiers D₁,D₃, …D_2n-1 shown in Fig. 6.4b operate and conduct during the positive half cycles while the rectifiers D₂,D₄,…D_2n conduct during the negative half cycles. Typical current and voltage waveforms of such a circuit are shown in Figs 6.4c and 6.4d respectively. The voltage on C₂ is the sum of the input a.c. voltage, V_ac and the voltage across condenser C₁,V_c1 as shown in Fig. 6.4.

The mean voltage on C₂ is less than the positive peak charging voltage (V_ac + V_c1). The voltage across other capacitors C₂ to C_2n can be derived in the same manner (i.e.) from the difference between voltage across the previous capacitor and the charging voltage. Finally the voltage after 2n stages will be V_ac (n₁ + n₂ + …), where n₁, n₂, … are factors when ripple and regulation are considered in the next rectifier. The ripple voltage δV and the voltage drop ΔV in a cascaded Voltage Multiplier Circuits unit are shown in Fig. 6.4e.

Ripple in Cascaded Voltage Multiplier Circuits:

With load, the output voltage of the cascaded rectifiers is less than 2nV_max, where n is the number of stages. The ripple and the voltage regulation of the rectifier circuit may be estimated as follows.

Let

• f = supply frequency,
• q = charge transferred in each cycle,
• I₁ =load current from the rectifier,
• t₁ = conduction period of the rectifiers,
• t₂ = non-conduction period of rectifiers, and
• δV = ripple voltage (peak to peak)

Referring to Fig: 6.3a, when load current I₁ is supplied from capacitor C₂ to load R_L during the non-conducting period, the charge transferred per cycle from the capacitor C₂ to the load during the non-conduction period t₂ is q, and is related as follows.

Since t₁ ≪ t₂ and t₁ + t₂ = 1/f (i.e. the period of the a.c. supply voltage),

Hence

At the same time a charge q is transferred from C₁ to C₂ during each cycle equal to I₁/fC₂. Thus the total voltage drop that occurs will be I₁/fC₁ + 2I₁/fC₂. Hence, regulation = mean voltage drop from 2V_max

Therefore, the mean output voltage

For the cascade circuit, on no load, the voltages between stages are raised by 2V_max giving an output voltage of 2nV_max for n stages.

Referring to Fig. 6.4b, to find and expression for the total ripple voltage, let it be assumed that all capacitances C₁,C₂,…,C_2n be equal to C. Let q be the charge transferred from C_2n to the load per cycle.

Then the ripple at the capacitor C_2n will be I₁/fC.

Simultaneously, C_2n-2 transfers as charge q to the load and to C_2n-1.

Hence, the ripple at the capacitor C_2n-2 is 2I₁/fC.

Similarly, C_2n-4 transfers a charge q to the load, to C_2n-3, and to C_2n-2.

Therefore, the ripple at capacitor C_2n-4 is 3I₁/fC.

Proceeding in the same way, the ripple at C₂ will be nI₁/fC.

Hence, for n stages the total ripple (peak to peak) will be

and the average ripple

The major contribution to the ripple is from the lowest or ground end capacitors, C₁,C₂,C₃,C₄, etc. Ripple can be reduced if the capacitance of these capacitors is increased proportionately i.e., C₁,C₂ are made nC,C₃,C₄ are made (n – 1) C and so on so that the total ripple will be equal to